1. Field of the Invention
The present invention relates to programmable devices such as field programmable gate arrays (FPGAs). More specifically, the present invention relates to methods for providing a programmable configuration interface to rapidly configure an FPGA.
2. Discussion of Related Art
Due to advancing semiconductor processing technology, integrated circuits have greatly increased in functionality and complexity. For example, programmable devices such as field programmable gate arrays (FPGAs) and programmable logic devices (PLDs) incorporate ever increasing numbers of functional blocks and more flexible interconnect structures to provide greater functionality and flexibility.
FIG. 1 is a simplified schematic diagram of a conventional FPGA 110. FPGA 110 includes user-programmable logic circuits (user logic) such as input/output blocks (IOBs), configurable logic blocks (CLBs), and programmable interconnect 130, which contains programmable switch matrices (PSMs). Each IOB and CLB can be configured through dedicated configuration port 120 to perform a variety of functions. Programmable interconnect 130 can be configured to provide electrical connections between the various CLBs and IOBs by configuring the PSMs and other programmable interconnection points (PIPS, not shown) through configuration port 120. Typically, the IOBs can be configured to drive output signals or to receive input signals from various pins (not shown) of FPGA 110.
FPGA 110 also includes dedicated internal logic. Dedicated internal logic performs specific functions and can be only minimally configured by a user. For example, configuration port 120 is one example of dedicated internal logic. Other examples may include dedicated clock nets (not shown), power distribution grids (not shown), and boundary scan logic (e.g. IEEE Boundary Scan Standard 1149.1, not shown).
FPGA 110 is illustrated in FIG. 1 with 16 CLBs, 16 IOBs, and 9 PSMs for clarity only. Actual FPGAs may contain thousands of CLBS, thousands of IOBs, and thousands of PSMs. The ratio of the number of CLBs, IOBs, and PSMs can also vary. Information regarding various types of FPGAs can be found in "The Programmable Logic Data Book" (hereinafter "The Xilinx 1996 Data Book"), published September, 1996 by Xilinx, Inc., and available from Xilinx, Inc., 2100 Logic Drive, San Jose, Calif. 95124.
FPGA 110 also includes dedicated configuration logic circuits to program the user logic circuits. Specifically, each CLB, IOB, PSM, and PIP contains a configuration memory (not shown) which must be configured before each CLB, IOB, PSM, or PIP can perform a specified function. Typically the configuration memories within an FPGA use static random access memory (SRAM) cells. The configuration memories of FPGA 110 are connected by a configuration structure (not shown in FIG. 1) to dedicated configuration port 120 through a dedicated external configuration access port (CAP) 125. A configuration port (a set of pins used during the configuration process) provides an interface for external configuration devices to program the FPGA. The configuration memories are typically arranged in rows and columns. The columns are loaded from a frame register which is in turn sequentially loaded from one or more sequential bitstreams. (The frame register is part of the configuration structure referenced above.) In FPGA 110, configuration access port 125 is essentially a bus access point that provides access from configuration port 120 to the configuration structure of the FPGA.
FIG. 2 illustrates a conventional method used to configure FPGA 110. Specifically, FPGA 110 is coupled to a configuration device 230 such as a serial programmable read only memory (SPROM), an electrically programmable read only memory (EPROM), or a microprocessor. Dedicated configuration port 120 receives configuration data from configuration device 230. Typically, configuration port 120 comprises a set of mode pins, a clock pin and a configuration data input pin. Configuration data from configuration device 230 is transferred serially to FPGA 110 through the configuration data input pin. In some embodiments of FPGA 110, configuration port 120 comprises a set of configuration data input pins to increase the data transfer rate between configuration device 230 and FPGA 110 by transferring data in parallel. However, due to the limited number of dedicated function pins available on an FPGA, configuration port 120 may have no more than eight configuration data input pins. Further, some FPGAs allow configuration through a boundary scan chain. Specific examples for configuring various FPGAs can be found on pages 4-54 to 4-79 of "The Xilinx 1996 Data Book," which pages are incorporated herein by reference.
As explained above, actual FPGAs can have thousands of CLBs, IOBs, PSMs, and PIPS; therefore, the amount of configuration data required to configure an FPGA can be measured in megabits. Because FPGAs are typically programmed serially or only minimally in parallel, configuring an FPGA after power-on or reset can take a significant amount of time. The configuration time for an FPGA is further lengthened because most configuration devices (e.g., SPROMS) have slow access times and slow data transfer rates. As FPGAs become even more complex, long configuration times may violate startup requirements in some systems after power-on or reset. Further, as the amount of configuration data increases, the cost of configuration device 230 may begin to impact the cost of the overall system using FPGAs. Hence, there is a need for a method and structure for rapidly configuring FPGAs while reducing the cost of any necessary configuration devices.